This invention relates to integrated circuits and, more particularly, to implementing loops in an integrated circuit.
Every transition from one technology node to the next technology node has resulted in smaller transistor geometries and thus potentially more functionality implemented per unit of integrated circuit area. Synchronous integrated circuits have further benefited from this development as evidenced by reduced interconnect and cell delays, which has led to performance increases. However, more recent technology nodes have seen a significant decline in the reduction of delays and thus a decline in the performance increase.
Solutions such as register pipelining have been proposed to further increase the performance. When implementing register pipelining, additional registers are inserted between synchronous elements, which lead to an increase in latency at the benefit of increased clock frequencies and throughput. However, performing register pipelining often involves spending significant time and effort because several iterations of locating performance bottlenecks, inserting or removing registers, and compiling the modified integrated circuit design are usually required.
Register pipelining is often also problematic for integrated circuits with feedback loop circuitry such as accumulation operations, infinite impulse response filters, phase-locked loop circuits, proportional-integral controllers, proportional-integral-derivative controllers, clock recovery modules, just to name a few.